SK Hynix Puts 100 Specialized Cores in One SSD Controller

Why Arm cores are hitting a thermal wall in SSDs

Traditional storage controllers rely on general-purpose Arm CPU cores to handle everything from background housekeeping to high-speed reads and writes.

As storage interfaces push past PCIe 5.0 toward PCIe 7.0 and PCIe 8.0, SSD controllers face an unsustainable power crunch. Every jump in bandwidth demands more processing power to parse commands, coordinate memory buffers, and update drive metadata. Sticking more general-purpose processor cores onto controller silicon increases die size and pushes thermal limits dangerously high inside dense server racks.

Speaking at the International SoC Design Conference, SK Hynix vice president Koo In-je stated plainly that general-purpose CPUs inside SSD controllers have reached their practical limits in both area and power consumption. The solution is not bigger compute clusters, but a total division of labor.

SK Hynix H-TPU controller specs compared to standard CPU cores

Inside the H-TPU: Tiny cores for predictable data paths

SK Hynix calls its custom silicon the Hynix Transaction Processing Unit (H-TPU). Rather than using an out-of-order execution engine packed with branch predictors, each H-TPU relies on a lean, four-stage sequential pipeline designed specifically for repetitive storage commands.

The trade-off delivers staggering efficiency gains. According to SK Hynix, a single H-TPU core consumes approximately 2.5% of the power drawn by a general-purpose processor core while occupying just 4% of the physical chip area. Over 100 of these micro-cores can sit on a single controller die without inflating the power budget.

The controller wakes individual H-TPU units on demand as incoming requests arrive and parks unused cores in deep sleep. Heavy lifting remains separate: conventional CPU cores stay on the controller die, but their workload is cut to exception management, error recovery routines, and drive-level policy decisions.

Paving the way for PCIe 8.0 and High Bandwidth Flash

The structural redesign directly targets incoming data center architectures. SK Hynix plans to roll out H-TPU designs across its enterprise SSD line, its broader AIN storage family, and its upcoming Storage Next architecture.

Storage Next is built to handle granular data transactions of 512 bytes or smaller, an eighth of the standard 4KB blocks traditionally used by storage drives. Modern artificial intelligence training clusters rely on these micro-transactions to shuttle parameters without wasted overhead, similar to how interconnect innovations like Marvell's optical memory pool aim to streamline enterprise pipelines.

SK Hynix also confirmed that the multi-core controller will accompany High Bandwidth Flash (HBF), an emerging high-density standard set to debut next year.

Availability and rollout

SK Hynix has not announced commercial deployment dates or enterprise pricing for drives featuring H-TPU controllers. The underlying High Bandwidth Flash hardware is scheduled to appear in 2027, meaning the first production controllers using the 100-core architecture are likely slated for enterprise qualification testing around the same timeframe across North American and European data center customers.